In the semiconductor technology field, board-level packaging is an advanced process suitable for ESD and MOS devices, as well as third-generation semiconductor SiC and GaN devices. It offers the advantages of high packaging component density and performance. Utilizing large-area fan-out wiring technology, the increasing wiring density and demand for more I/O ports in the semiconductor industry have jointly driven the development of Fan-Out packaging.

Compared to other packaging methods like Wafer-Level Chip Scale Packaging (WLCSP), the main distinction of board-level packaging lies in the substrate. It shifts from using 8-inch/12-inch wafer carriers to large-format rectangular panels. This shift allows board-level packaging to adapt to a broader range of application scenarios, particularly complementing WLP in mid- to low-end applications. As technology advances, board-level packaging is progressively moving into more refined market segments, such as those requiring line widths below 10µm, while maintaining cost advantages. Based on this technology, higher packaging component density and performance can be achieved.

Underfill Process
Underfill refers to the technology of filling the space between an integrated circuit chip (die) and the package substrate, another chip, or an interposer with a polymer (resin)-based composite material to enhance package stability.

The basic principle involves dispensing adhesive along the edge of the flip-chip. Through "capillary action," the adhesive rapidly flows into the underside of the BGA chip. The minimal space for this capillary flow is typically around 10µm, which aligns with the low electrical characteristic requirements between solder pads and solder balls in the soldering process (the adhesive won't flow into gaps smaller than 4µm, ensuring the electrical safety characteristics of the soldering process).

The adhesive is drawn to the opposite side of the component, completing the underfill process. It is then cured by heating. After thermal curing, it forms a strong adhesive and filling layer, reducing thermal stress mismatch caused by differences in the coefficient of thermal expansion between the chip and substrate. This improves the structural strength and reliability of the device and enhances the drop resistance between the chip and substrate.

Therefore, board-level packaging underfill is a critical process step. It requires consideration not only of PCB design and material selection but also strict control over the process to ensure filling effectiveness and product reliability.

Quark Technology: Pursuing Perfection
The piezoelectric jet valve, with its advantage of precise regulation via piezoelectric drive units enabling fast, accurate, and sustained operation, was adopted by the customer. Its performance was rigorously tested across multiple rounds, focusing on speed, accuracy, stability, and dispensing results.

For the semiconductor underfill process, the customer tested three different valves from domestic and international suppliers, including Quark's valve. Quark Research Institute's meticulous one-stop technical R&D and production service, along with superior solution design capabilities, earned the customer's favor and trust. They chose to implement Quark's high-precision piezoelectric jet valve for the Underfill process.

The high-precision piezoelectric jet valve employs advanced piezoelectric ceramic actuation technology. It achieves a dispensing accuracy of ±1% and a minimum single-droplet volume of 0.1 nl. It meets the customer's critical process requirements for thermosetting adhesives, including heating and insulation, uniform filling and diffusion, absence of splatter and bubbles, and achieving an extremely narrow glue bleed width.

Underfill Process Requirements:

• Splatter rate: 3 per 10,000

• Dispensed adhesive weight: 1mg, 3mg, 5mg, with error controlled within +3%

• No breakage, insufficient adhesive, or splatter in drawn lines

• For 1mg across 200 dots: +5% error, CPK > 1.67

Leveraging years of accumulated manufacturing experience and process expertise, Quark Research Institute conducted comprehensive optimization of the structure and functional parameters of key components. Its independently developed piezoelectric valve effectively addresses issues of adhesive stringing and splatter with thermosetting adhesives, achieving a splatter rate of 3/10,000 and significantly improving CPK.

• Maximum jetting speed of 1000 times/second ensures high-efficiency dispensing.

• Advanced heating components enhance adhesive flowability, improving dispensing efficiency.

• Precise temperature control ensures high yield rates.

• Leading valve control logic guarantees uniform adhesive lines, free from breaks, insufficient adhesive, overflow, or splatter issues.

China's semiconductor industry faces multiple layers of barriers) in the international landscape. The localization of semiconductor equipment can not only enhance domestic technological capabilities but also help domestic enterprises improve their international competitiveness from the perspective of cost reduction and efficiency improvement. Quark Research Institute is committed to the R&D of core dispensing components and providing localized services. We aim tohelp break through the challenges for the domestic semiconductor industry with high-precision fluid control technology!